IBM unveils sub-1nm chip prototype using 'block of flats' design
Tags Infrastructure · Hardware
IBM announced the world's first known chip technology below 1 nanometer, using a novel 'block of flats' (vertical transistor stacking) design that could extend Moore's Law by another decade. The prototype, while years from commercial production, demonstrates a viable path beyond current EUV lithography limits. The breakthrough uses a complementary field-effect transistor (CFET) architecture stacked vertically rather than scaling horizontally. If successfully commercialized, it would enable continued transistor density improvements even as traditional lithography scaling slows.
Technical significance
Vertical transistor stacking represents the most promising near-term path to continued density gains beyond EUV limits. For the industry, this validates the CFET approach that Intel, TSMC, and Samsung have been researching. However, the years-to-production gap means current 2nm/1.4nm roadmaps remain the relevant planning horizon for chip designers and system architects.