IBM unveils world's first sub-1-nanometer chip technology with 100B transistors
Tags Infrastructure · AI · OSS
IBM announced its 'nanostack' transistor architecture, which it calls the world's first sub-1-nanometer chip technology, packing nearly 100 billion transistors on a chip the size of a fingernail. The architecture, built at what IBM terms the 0.7-nanometer (7 angstrom) node, vertically stacks transistors in a staggered layout and could deliver 50% higher performance or 70% greater energy efficiency than IBM's 2nm technology. It also achieves a 40% improvement in SRAM scaling — critical for AI workloads — where previous generations saw only single-digit improvements. IBM presented the work at the 2025 IEEE VLSI Symposium in Kyoto.
Technical significance
The 40% SRAM scaling improvement is arguably more significant than the transistor density gain for AI workloads, since SRAM bandwidth has become the primary bottleneck for transformer inference. IBM's nanostack approach — vertical stacking rather than lateral scaling — signals the industry's transition to 3D transistor architectures as the primary path beyond 2nm. Commercialization timeline remains years out, but the SRAM result alone could influence next-gen AI accelerator designs.